In a data processing system, data may be received or transmitted via an input/output (I/O) interface. This may be an I/O controller interface to an off-chip data resource or a network interface controller (NIC) to a resource of a local or remote network.
When data is received from an I/O interface it is directed to a storage resource of the data processing system. Selection of which storage is to be used may be controlled by software or hardware configuration of the data processing system. However, this approach is not optimal since the usage of the received data is difficult to predict. As a result, data directed to a memory device may need to be moved at once to a processor cache for use, resulting in additional memory transfers, while data stored directly in a cache, via a cache stashing mechanism for example, may not be needed, wasting cache space and requiring additional memory transfers to evict the data back to memory.
A data processing system may be arranged as a network, such as network on a chip, that includes a number of nodes coupled via an interconnect structure. Data transfer in and out of the network is controlled by one or more input/output (I/O) interfaces that provide access to an off-chip data resource. Data is transferred between a processing node of the network and the I/O interface via the interconnect structure.
Since an interconnect structure has limited bandwidth, some data transfers may be delayed. Performance of the data processing system may be degraded when a time-critical data transfer is delayed. One approach to mitigating this problem is to use an interconnect structure that enables a processing node to prioritize transfers. For example, a software instruction issued by a processing node to access data at a particular address may include an argument indicative of the priority of the access.
This approach is ineffective, however, since a user may not be able to determine in advance what the priority should be. There will be a tendency for a user to make all requests high priority.